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TI Readies DDP 2000 ASIC

08.27.2003

Texas Instruments (Plano, TX) (www.dlp.com) used a private suite at InfoComm to brief us on developments of its newest controller ASIC, the DDP2000. This controller will integrate additional functionality and is aimed at the low-cost front-projection market. TI expects to begin production in August, assuming everything is fine with the design verification. This could lead to projection products by the end of the year.

At InfoComm, TI showed the first silicon samples of the new ASIC. It is designed for use with the 0.7-inch DDR XGA resolution or 0.55-inch SVGA resolution DMDs. It consolidates a separate DMD controller chip and de-interlace chip within the DDP2000, but still needs to be used in conjunction with the DAD 1000 waveform generator.

TI's own DSP-based core is used for scaling, deinterlacing, and 3:2 and 2:2 pull down. It integrates an ARM processor and can do 1-D keystone correction.

Compared to a projection electronics board solution circa year 2000, the DDP2000 solution will be about 50% of the cost and 50% of the volume.

It will be packaged in a 564-pin BGA and will need a 128 MB DRAM. An SRAM is optional. It was integrated into a 5" x 4" PCB, which should shrink to around 3" x 4" in production.

Texas Instruments, Ian McMurray, [44] 1604-663075, i-mcmurray@ti.com

Contact:
Insight Media
Annmarie Gabisch, 203-831-8464
annmarie@insightmedia.info

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